Seeking a highly motivated and innovative engineer. Working as part of a highly experienced emulation team, the candidate will be contributing towards improving the quality of Synopsys Emulation product Zebu. The position offers an excellent opportunity to work with an expert team of emulation engineers & architects responsible for qualifying emulation product from specification development to performing functional and performance tests for validating the backend methodology for Emulation tool. In addition, this is a great opportunity to work with a wide suite of in-house digital design and verification tools, including VCS, Verdi as well as Xilinx FPGA Vivado tool. Role would also provide opportunity to verify and create debug solutions for customers for complex emulation problems.
Responsibilities of this job include
The candidate will be responsible for validation of Emulation product (ZeBu) and various backend flows and product solutions for emulation. The Engineer will also design and develop tests in VHDL/Verilog/System Verilog languages, resolving synthesis and place & route with FPGA to validate the tool. Responsible for analyzing customer designs & in-house, modifying block-level test benches, executing verification plans, analysis/debugging RTL and gate-level emulation failures, performing gate-level emulations, interacting with R&D and CAE teams. Candidate will also be responsible for developing validation strategy and coverage driven plan for newer solutions and take it to production working with R&D and AE teams.
The successful candidate will have B. Tech/M. Tech in EEE/ECE/ETE/VLSI engineering with 2-5 years hands-on experience in emulation/simulation. Knowledge on areas like Synthesis, Simulation, Verification, place and route with FPGA is preferred. Knowledge and experience on Hardware emulation tool or experience in verification technology, testcase creation, simulation using VCS or other simulators, debugging with Verdi/DVE is must. Must be proficient multi-taskers to ensure all aspects of engineering a product are addressed. Familiarity with scripting languages, verification IP protocol are a plus. Should have good organization and communication skills for interacting with R&D and CAEs teams.